IBM Packs Nearly 100 Billion Transistors Into a Fingernail-Sized, Sub-1 Nanometer Chip by Stacking Them in Layers
Engineers at IBM crossed a long-standing boundary in semiconductor design this week. They produced working technology for chips with features smaller than one nanometer by arranging transistors in vertical stacks rather than laying everything out on a single flat plane. The nanostack technique is the most recent iteration of IBM’s nanosheet transistors, which have been [...]
Engineers at IBM crossed a long-standing boundary in semiconductor design this week. They produced working technology for chips with features smaller than one nanometer by arranging transistors in vertical stacks rather than laying everything out on a single flat plane. The nanostack technique is the most recent iteration of IBM’s nanosheet transistors, which have been [...]
Share
What's Your Reaction?
Like
0
Dislike
0
Love
0
Funny
0
Angry
0
Sad
0
Wow
0
